This invention relates to communications systems and methods, in particular, to Phase-Locked Loops.
Phase-Locked Loops (PLLs) are commonly used for synthesis of a smoothed clock from an irregular or jittered input clock. The smoothed clock runs at the frequency of the input clock but does not contain the some or all of the jitter present in the input clock signal. FIG. 1 shows a block diagram for a basic PLL.
A PLL like that shown in FIG. 1 is a linear system. The Phase Detector 108 measures the difference between the phase of the Input Clock 104 and the phase of the Output Clock 128. This difference, known as Phase Error 112, is then passed through a Low Pass Filter (LPF) 116 that attenuates the high-frequency components to produce a Filtered Phase Error 120. (One type of low pass filter is sometimes called an xe2x80x9cintegratorxe2x80x9d.) The Filtered Phase Error 120 is then fed into a Voltage-Controlled Oscillator (VCO) 124. The Output 132 of the VCO 124 is fed back to the Phase Detector 108 as the Reference Clock Value 140, after passing through a Divider 136. The Divider adjusts the frequency of the Reference Clock Value 140 to match the frequency of the Input Clock 104 as is necessary when the frequency of the Output 132 of the VCO 124 is set to be an integer multiple of the Input Clock frequency.
This type of system is a feedback system, and when operating properly it tends to drive the Phase Error 112 to zero (or some small value) and the Output Clock 128 will track the Input Clock 104, or at least the desired frequency components thereof.
FIG. 2 shows a typical PLL application. The jittered Input Clock 104 is used to clock Input Data 206 into the FIFO Buffer 208. It is also used as an input to the PLL 204, which provides a smoothed clock as an output 128. The smoothed Output Clock 128 is also used to clock xe2x80x9csmoothxe2x80x9d Output Data 210 out of the FIFO Buffer 208 that is being used as a buffer to absorb jitter from jittered Input Data 206.
A PLL has a number of parameters that are selected at design time:
Gain of the phase detectorxe2x88x92KP 
Gain low pass filter (LPF)xe2x88x92KF 
Gain of the Voltage Controlled Oscillator (VCO)xe2x88x92KV 
Natural frequency of the low pass filterxe2x88x92xcfx89N 
The divide by value used in the dividerxe2x88x92N
The parameters control the PLL""s operational characteristics as follows:
Frequency response and cutoff frequency: FC=xcfx89N/2xcfx80
Transient response and settling time: Ts≈1/(2*FC)
Steady-state phase error: E=Fin/[Fcenter(1+K)] where Fcenter is the nominal frequency of the VCO.
Tracking range: R=R0/(1+K) where R0 is the nominal range of the VCO.
These operational characteristics are all inter-related. Thus, changing one parameter tends to change more than one of the operational characteristics. The design and operation of Phase-Locked Loops is within the skill of one of ordinary skill in the art. General information on this topic is readily available and thus will not be described here in any detail. Textbooks describing the design of Phase-Locked Loops include 1) Floyd Martin Gardner, xe2x80x9cPhaselock Techniquesxe2x80x9d, John Wiley and Sons, ISBN: 0471042943; 2) Roland E. Best, xe2x80x9cPhase-Locked Loops: Design, Simulation, and Applicationsxe2x80x9d, McGraw-Hill Professional Publishing, ISBN: 0071349030; and 3) John J. D""Azzo, xe2x80x9cLinear Control System Analysis and Designxe2x80x9d, McGraw-Hill, ISBN 0070161836.
The values are chosen based on knowledge of the input signal as well as the system requirements. The choice of the design parameters affects the performance of the PLL in such areas as stability, acquisition and tracking bandwidth and noise rejection. Fixed (xe2x80x9cstaticxe2x80x9d) parameters mean that the PLL may not be operating in the optimal fashion as the characteristics change for the input signal.
A linear control system like a PLL can be highly optimized when the characteristics of the input signal vary only slightly. A system that worked fine for one type of input signal may not work well as the input changes. A dynamic system allows the PLL to treat the varying input in a piecewise linear fashion, giving optimum performance in each set of input conditions.
The range of values on the input signal may exceed the dynamic range of some of the PLL components. In this case, a system with fixed parameters might not work at all in some situations. A dynamic system can overcome this limitation.
Some of the PLL parameters affect multiple performance metrics such that improving one metric has a deleterious affect on another metric. For example, acquisition range and noise rejection are usually inversely proportional. A dynamic system can increase the noise rejection in the domains where the input is well behaved, and a wide acquisition range is therefore not needed.
Prior art designs fixed the values of the PLL parameters so the PLL was optimized for one set of input conditions. In some cases specialized PLLs had more than one set of fixed PLL parameters for the PLL to operate in two different modes. For example, the prior art includes the concept of a PLL that uses a more stringent set of parameters for clock signal tracking after the PLL locks onto a clock signal. This is switching the mode of operation of the PLL to perform a different function (signal tracking versus signal acquisition).
Likewise some PLLs are adapted to work with two or more different frequencies of different values. Again, the PLL can be set to one mode or another based on the frequency that is expected, but the PLL does not have dynamically adjusted parameters to react to changes in the behavior of the expected input. More specifically, if the jitter associated with an input signal changes over time, the PLL does not react by changing PLL characteristics to adjust for the increased jitter.
In February of 2002, Altera Corporation announced a new programmable logic device, the Stratix(trademark). This device has extended support for phase-locked loops. The features include PLL reconfiguration that gives designers flexibility in multiplying or dividing input clock frequencies to achieve higher or lower output clock frequencies and allows real-time variations of the PLL frequency and output clock skew. StratixTM frequency synthesis and programmable delay features can be changed by users on-the-fly; for example, designers can modify the PLL output frequencies and clock delays in prototype environments. This feature allows for PLL reconfiguration without reprogramming the rest of the chip. Furthermore, during system debugging, users can change the certain PLL parameters to optimize the system timing.
However, while a designer has additional control over frequency and clock skew, Altera documentation specifically excludes dynamic adjustment of the PLL loop filter components. Thus, although the Altera device facilitates development of PLL functions on a programmable logic device, it does not support or suggest the use of dynamic control of PLL parameters to adapt to changes in the characteristics of a received clock signal.
It is therefore an object of the invention to provide dynamic control of a PLL based on the real time characteristics of the input signal.
Several versions are disclosed of a Phase-Locked Loop with a control system to provide dynamic automatic adjustment to changes in one or more characteristics of the Phase-Locked Loop in response to changes in the jitter level of the input. These Phase-Locked Loops are responsive to changes in the input to the Phase-Locked Loops so that the operation of the Phase-Locked Loops can more closely approximate optimal settings for various levels of input jitter. One version of the invention compares a monitored jitter value against control state set points and upon detection of movement across a set point, changes one or more operating parameters of the Phase-Locked Loop. Various versions of the invention use different inputs and modify different operating parameters in order to achieve the objective of an automatic dynamic alteration of a Phase-Locked Loop in response to a change in jitter level of the input.
A version of the disclosed invention can be used as part of a circuit emulation system to receive circuit emulation payloads. In this version of the invention, the phase detector portion of the PLL is the jitter absorption buffer and the PLL uses a filtered jitter absorption buffer depth to vary the clock speed. This version of the invention uses a periodic sample of the difference between the highest and lowest levels of the jitter absorption buffer as a metric for network conditions. This metric is used by the control system to select the appropriate set of parameters for use by the PLL.